More and more difficult processes, fast and fast design, where is the future? As a director in the business, Intel also has a new and more flexible way to recommend & It is preparing new CPUs, GPU architecture and materials.
At the Architecture Day event,Intel revealed a new 3D identity packet technology called "Foveros", which introduced 3D steel design for CPU editors for the first time. It can bring solid teams on slates and bring together a series of different processes, structures and practices. The second half of 2019 started.
Intel said that technology is providing great flexibility, designer patent models can mix different technology, different memory fragments, I / O configuration in new product format, and enable them to The product is less broken "Skin mixing."
Intel first reviewed the problems of a new process in recent years, especially for high-performance computing teams. The 14nm process has been used for four years, which was not easy to do in the past.
However, not just any Intel processes, but optimizations are different for different uses of the skeleton, since the I / O chipset has, in fact, been changing.
For the next generation of process planning, Intel has three levels, initially for a 1274 10nm process, which will be developed for 1274.7, 1274.12 (10nm +, 10nm ++), and for I / O there are 1273 for new Foveros. Then P1222 is designed and no further development needs to be in the short term.
Then, the computer team will enterà
1276 7nmThe process generation, IO, Foveros will also change at the same time, and for the futureà
1278The fast computing process is still under review, and an accident should not be equal to 5m.
According to Intel, the demand for cross-attractive congestion is quite different for different criteria or active modules. The performance, the power to use and its; cost is very different too. So, all the fast modules that use the same process, do not reach the best results, especially the new process. It's getting harder and harder, it's not worth it, and it's a bit. becoming harder and harder.
Intel was previously launchedà
EMIB (Intermittent Interconnection Bridge) 2 Embossing TechnologyFor this purpose, the normal product is the Kaby Lake-G process that is a key link of the graphics of AMD Vega GPU.
Foveros has been updated to a 3D pack, which converts the multi-prompt from one plane to a stereo mix, which is a great deal. Increase integration density and allow a more flexible mix of chips or active modules.
This is the 3D 3D 3D Foveros 3D 3D video diagram:à
At the bottom, the flag state, which has a basic thread (Bottom Chip) is set, which acts as an active interposer.– AMD Fiji / Vega has the same basic folder of HBM memory.
A variety of new materials or modules can be placed on the top of the intermediary series., such as CPU, GPU, memory, baseband …
There is a large number of TSV 3D silicon walks in the interposerThere will be a responsibility for the binder to bend up and down, and then; allowing the high skirt and the module to communicate with other parts of the system.
There is already a sample of Foveros slates at Intel, and said it's ready for a big representation.Next year, the first release will be launched, the small person above is cited Intel"Hybrid x86 Process" (Hybrid x86 CPU)South Westerly
This little skipà
The length and width is only 12 x 12 mm and is only 1 mm.There is still no base, but there is a 3D stack inside which many modules can be closed.
Above the bottomà
IO skip of the P1222 22FFL process (type of work 22nm)Low cost and low burn.
The P1274 10nm computer cabinet, also known as a traditional CPU, also incorporates Sunny Core's high performance core and four Atom's four low power caps (and possibly the new Tremont architecture).
Continue up longerà
PoP Single-Limited Memory PipeSouth Westerly
Intel says thatIts energy consumption is only 2mW, which is 0.002W, and the power volume is not greater than 7W.It is clear to the mobile platform, and there is no need for a fan, but the special target device did not say.
Look at the inside part of this process: the top right corner of the single Sunny Cove CPU band, with a 0.5MB 0.5MB half-cache MLC 0.5MB, is in the corner The left-hand table is the LPDDR4X regulator, the width of four four × 16-bit spaces, and four small Core CPUs that have a 1.5MB division of the L2 archive.
In the middle there is a 4MB final archive, & # 39; the lower section is distributed by a low power convert of the 11th generation (64 EU units), a generator of 11.5 generation display, DisplayPort 1.4 controller, and other modules.
However, the online showcase prototype platform also uses a small fan, as well as a # 39; see PC.2-M M.2 interface, UFS flash memory, several SIM connections –à
Does Intel want to enter the mobile phone process?
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